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Window watchdog (WWDG)
RM0008
18.4
How to program the watchdog timeout
Figure 160 shows the linear relationship between the 6-bit value to be loaded in the
watchdog counter (CNT) and the resulting timeout duration in milliseconds. This can be
used for a quick calculation without taking the timing variations into account. If more
precision is needed, use the formulae in Figure 160 .
Warning:
When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
Figure 160. Window watchdog timing diagram
T[6:0] CNT downcounter
W[6:0]
3Fh
time
Refresh not allowed
Refresh window
T6 bit
Reset
The formula to calculate the timeout value is given by:
T WWDG = T PCLK1 ? 4096 ? 2
WDGTB
? ? T ? 5:0 ? + 1 ?
; ? ms ?
where:
T WWDG : WWDG timeout
T PCLK1 : APB1 clock period measured in ms
Min-max timeout value @36 MHz (PCLK1)
18.5
WDGTB
0
1
2
3
Debug mode
Min timeout value
113 μs
227 μs
455 μs
910 μs
Max timeout value
7.28 ms
14.56 ms
29.12 ms
58.25 ms
When the microcontroller enters debug mode (Cortex-M3 core halted), the WWDG counter
either continues to work normally or stops, depending on DBG_WWDG_STOP configuration
bit in DBG module. For more details, refer to Section 29.16.2: Debug support for timers,
watchdog, bxCAN and I 2 C .
406/995
Doc ID 13902 Rev 9
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